How a Solid-State Transformer Works: SST in 800 VDC Data Centers
Stage-by-stage working principle of the solid-state transformer - cascaded H-bridge rectifier, dual active bridge isolation, direct 800 VDC output - with the Faraday arithmetic, chain efficiency, capex and the honest open problems.
The last article on this blog walked through NVIDIA's 800 VDC distribution architecture and ended with a four-stage adoption table in which the final stage — a solid-state transformer taking medium voltage straight to the 800 VDC bus — was marked as the most speculative[1]. It deserves more than one line, because the solid-state transformer (SST) is the piece that turns the 800 VDC data center from "an AC plant with a big rectifier" into what it is really supposed to be: a DC machine fed directly from the grid.
This article explains how an SST actually works — not as marketing physics but stage by stage, with the switching topologies, the arithmetic that makes the transformer shrink, and the numbers a buyer can check. It also covers what the SST buys beyond efficiency, what it costs, and the four engineering problems that still stand between today's 98%-efficient lab units and the 99%+ production systems the industry has promised. The companion piece on the 800 VDC architecture covers why the industry wants a 800 V bus in the first place; this one is about the box that creates it.
Why the iron transformer is the last passive device in the chain
Every other element of a modern power train — rectifier, UPS, DC-DC converter, VRM — is already a switching power supply. The one exception is the machine that connects the building to the grid: a line-frequency transformer (LFT), essentially unchanged in principle since the 1880s. It steps 13.8 kV AC down to 480 V AC by magnetic induction at 60 Hz, which dictates everything about it.
The sizing rule comes straight from Faraday's law. For a sinusoidal winding voltage, the flux-carrying product of turns and core cross-section is fixed by voltage, frequency, and allowable core flux density:
The Faraday arithmetic that drives the whole SST story. Raise the switching frequency three hundredfold and the magnetic core shrinks by the same factor in theory; winding window, insulation, and thermal limits cut the realized gain to roughly 10-14x, which is exactly what Infineon quotes — 14x smaller and 40x lighter than the equivalent line-frequency unit[8].
That arithmetic has two consequences. First, the passive transformer itself becomes small enough to hold in two hands: a 2.5 MVA dry-type unit weighs roughly 4.5 tonnes, while an SST of the same rating lands near 112 kg at the quoted 40x reduction[8]. Second — and more important than size — the device that replaces the transformer is now made of controlled switches. A transformer transforms whatever the grid gives it; an SST decides, millisecond by millisecond, what its output should be. Everything the SST is valued for beyond efficiency follows from that single change.
Stage 1 — the medium-voltage rectifier: cascaded H-bridges
Connect 13.8 kV to a semiconductor and it dies: the line-to-line peak is 19.5 kV, and the phase-to-neutral peak a single phase sees is 11.27 kV. The best silicon carbide MOSFETs in volume production block 3.3 kV[5] — a factor of four short. The SST does not wait for 10 kV devices; it stacks proven ones in series.
The standard input stage is a cascaded H-bridge (CHB) rectifier. Each module is a small four-switch bridge with its own isolated DC link, and the modules are connected in series on the AC side so their voltages add up to withstand the medium voltage while each module individually only ever sees its own 1.8 kV share. The active bridges are phase-shifted so the synthesized input waveform is a smooth multilevel staircase — that is also what gives the SST its excellent grid behavior: the input current is drawn sinusoidally at near-unity power factor, with the harmonic content of a well-behaved PFC stage rather than a six-pulse rectifier[4].
The stacking arithmetic. Each added module buys insulation coordination and redundancy; fewer, larger modules are the single biggest lever on cost, which is why the 3.3 kV and next-generation 10 kV SiC roadmaps matter so much[4][5].
Why series, not one big switch? Because series-connected modules — each with its own transformer, its own control loop, and its own thermal budget — fail gracefully. If one module faults, its bypass contactor closes and the SST derates by 1/21 instead of going dark. ETH Zurich's system studies identify this modularity, and its cost in duplicated insulation and duplicated magnetics (the "modularization penalty"), as the central design tension of the whole technology[2].
Stage 2 — the dual active bridge: where the "transformer" actually lives
Between the module DC links and the output sits the stage that gives the SST its name: a dual active bridge (DAB) converter driving a compact medium-frequency transformer. Two full bridges — one on each side of a small ferrite or nanocrystalline transformer — chop their DC voltages into square waves and feed each other through the transformer's own leakage inductance. No separate inductor is needed; the leakage inductance that a 60 Hz designer spends effort minimizing is here the intentional power-transfer element[9].
Control is by phase shift. The two bridges run at the same frequency, and the power transferred is set by the phase angle between them:
The DAB operating point. At 50 kHz the eight switches per module never switch hard: the phase-shift sequencing discharges device capacitances before each turn-on, giving zero-voltage switching (ZVS) across the load range, which is what allows the frequency to be high without the switching losses being prohibitive[9].
Two properties of this stage deserve emphasis. First, the medium-frequency transformer provides galvanic isolation exactly as a 60 Hz unit does — the utility side and the data center side remain separate circuits — but its core is a 45 mm ferrite block instead of a 141 mm steel stack, per the Faraday numbers above. Second, because the bridges on both sides are fully controlled, the stage is bidirectional by construction: power flows MV-to-LV or LV-to-MV with no hardware change, only a sign change in the control angle[4].
Stage 3 — the output: a DC bus, not an inverter
In grid applications the SST's third stage re-inverts to AC. In the data center application, the punchline is that there is no third inversion: the module outputs are connected in parallel on an 800 VDC bus — the ISOP arrangement (input-series, output-parallel) that Navitas's reference architecture shows converting 13.8 kV or 34.5 kV MVAC directly to 800 VDC[4]. The input series stack handles the medium voltage; the output parallel bank handles the current. From that bus, the downstream chain is the now-familiar one — sidecar or row-level LLC converters stepping to rack voltage, then 64:1 stages to the GPU cores — which the previous article walked through in detail[1].
Batteries and supercapacitors connect to the same 800 V bus through their own bidirectional DC-DC stages, which is why the SST architecture absorbs the UPS: energy storage rides the same DC link the IT load rides, with no double conversion and no separate battery inverter[1].
The efficiency arithmetic a buyer can check
Vendors quote SST system efficiency targets of 97% to above 99%[6][8]. The honest way to evaluate that is to compare like with like: the grey-space segment both architectures must perform — 13.8 kV AC in, 800 VDC out.
| 13.8 kV to 800 VDC segment | Stages | Segment efficiency | Heat per MW delivered |
|---|---|---|---|
| Conventional: LFT + LV switchgear + centralized rectifier | 0.992 x 0.999 x 0.975 | 96.62% | 34.9 kW |
| SST (direct MV to 800 VDC) | 0.985 | 98.5% | 15.2 kW |
Segment arithmetic per MW delivered. The 19.7 kW difference is worth about $17,300 per MW-year at $0.10/kWh, or $17.3 million per year across a 1 GW campus — before counting the eliminated UPS losses, floor space, and cooling air.
Those segment numbers use a deliberately conservative 98.5% SST. What has actually been measured: ETH Zurich's 25 kW 3.8 kV AC to 400 V DC laboratory SST reached 98.1% end-to-end as early as 2018 — at the time, half the losses of comparable units[3] — and the same group's 400 kW, 13.2 kV-to-800 VDC prototype presented at INTELEC 2025 holds today's public benchmark at 98.0%, with 98.0-98.5% regarded as the state of the art for full-scale units and 99% the next engineering target[2]. On the product side, SolarEdge and Infineon are jointly validating a modular 2-5 MW SST building block targeting above 99% for exactly this MV-to-800-1500 VDC role[6]. One widely cited estimate credits the full-chain improvement — SST plus the removal of legacy conversion stages — with lifting the wall-to-compute efficiency path from roughly 82-85% to 97% or more[8], and NPC Electric calculates that the efficiency gain alone saves 87 MWh per year for a 1 MW facility loaded at 20%[7].
Keep the comparison honest in both directions. The SST is not automatically the most efficient option on the table. ETH Zurich's comparative evaluation found that a conventional line-frequency transformer paired with a SiC rectifier can match SST efficiency and functionality — the SST has to earn its extra two points of segment efficiency against an improved incumbent, not against a 1980s install base[2]. The case for the SST therefore rests on efficiency plus everything the switches enable, which is the subject of the next section.
What solid-state actually buys: the transformer becomes software
Efficiency is the headline, but it is the least differentiating item on the list. The real product is controllability:
- Voltage regulation as a control loop. An LFT's output voltage moves with load and grid conditions per its impedance; the SST holds its 800 V bus to setpoint regardless, reacting in milliseconds. That matters directly for AI training loads, whose power draw steps violently between phases — the same transient problem that drives UPS sizing in our battery backup calculation guide, handled here at the source instead of at the rack.
- Power quality on both sides. The CHB input draws sinusoidal current at unity power factor, and the same controlled bridges can inject reactive power or cancel harmonics for the local grid. The SST is, in effect, an active filter it would otherwise have to buy — a meaningful overlap with the harmonic budgeting described in our power quality article[7].
- Bidirectional and multi-port operation. Because every stage is a controlled bridge, the SST routes power in either direction: charging battery storage, exporting during demand response, or aggregating PV, fuel cells and the grid onto one DC bus with software-defined routing. That capability is what pushes grid-interconnected SSTs toward distributed-energy-resource classification under IEEE 1547 and IEEE 2800, which prospective operators should scope early[8].
- Fault current limiting. The switches can throttle current far faster than any protective device can clear, enabling the electronic fault isolation that a purely passive transformer cannot offer.
- Footprint and weight. Roughly 50% of the floor space for the transformer-to-bus segment, and an order-of-magnitude weight reduction — which matters less in a greenfield hall than it does in retrofits, upper floors, and on ships[7].
What it replaces, and what it costs
The SST consolidates a whole equipment chain. Analysts estimate the displaced gear at roughly $0.55M per MW of LV distribution equipment plus $0.20M per MW of Phase-2 rectification, against SST pricing of about $1.0-1.5M per MW — meaning first deployments arrive at an upfront premium of roughly $0.25-0.75M per MW, recouped through efficiency, floor space, and the collapsed installation schedule[2].
| Function | Conventional chain | SST architecture |
|---|---|---|
| Voltage transformation 13.8 kV to LV | Line-frequency transformer (tonnes, passive) | 21 stacked DAB modules (~112 kg class) |
| Rectification to DC | Centralized rectifier hall | Built into stage 1 |
| Galvanic isolation | 60 Hz iron core | Medium-frequency ferrite core per module |
| Energy storage interface | UPS + battery inverter, AC-coupled | Bidirectional DC-DC on the 800 V bus |
| Power factor / harmonics | Active filters, capacitor banks | Controlled by the input bridges |
| Voltage regulation | OLTC tap changers, seconds | Control loop, milliseconds |
| Capacity growth | Transformers sized in steps | Add modules |
Table 2 — What consolidates into the SST, function by function. The right-hand column is one product category instead of five, which is itself part of the value: one vendor, one control plane, one spare-parts pool.
The four problems that have not been solved yet
An honest SST article has to end this section somewhere short of "order yours now." Four issues separate the lab benchmark from the production fleet:
- Reliability data does not exist yet. A passive transformer is a 30-40 year device; no SST vendor has published field reliability data at data center scale. The longest-running power deployment of comparable technology is a Hitachi-ABB unit on the Swiss Federal Railways, operating since 2011 — encouraging, and not a data center[2]. Meanwhile the failure surface has moved from two windings to 252 semiconductor junctions, which is why module-level redundancy and bypass are design requirements, not options[9].
- Heat is concentrated, not dispersed. The LFT's 8.1 kW per MW of loss leaves passively through its tank walls. The SST's 15.2 kW must be actively pulled out of semiconductor junctions — liquid cooling in most reference designs, proprietary air-cooled insulation in others. The cooling system is now a series reliability element of the power chain, with fans and pumps on the critical path[2][8].
- The device roadmap is the schedule. Data-center-scale SSTs lean on 3.3 kV SiC MOSFETs in volume production and, for the next density leap, 10 kV-class devices that are still maturing; GaN, capped near 650 V, serves only the downstream stages[2][5]. FREEDM Systems Center's demonstration of 210 kHz switching on 3.3 kV SiC toward a 99% modular DC-DC target shows the headroom — and shows it is still academic[2].
- Protection and standards are catching up. DC faults have no natural current zero, so the SST needs coordinated solid-state or hybrid breaking — one of the open problems the 800 VDC architecture article flagged, now being addressed with dedicated SiC-based DC breaker development alongside the SST platforms[1]. Grid-interconnected, bidirectional units additionally pull IEEE 1547/2800 interconnection obligations into scope[8].
Where deployment actually stands
The vendor landscape has consolidated around two product paths that converge on the same 800 VDC output. LV-input SST skids (3.2-4.8 MW) keep the site's existing MV transformer and deploy behind it today, trading some of the theoretical gain for a much shorter time-to-deployment; MV-input units collapse the transformer and rectifier into one device as 3.3 kV-class SiC supply scales[2]. DG Matrix — the only SST included in NVIDIA's MGX reference architecture — is shipping pre-certification units with UL certification targeted by the end of Q2 2026; Amperesand targets 30 MW of commercial deployments in 2026; Heron Power is building a 40 GW US manufacturing facility around its 4.2 MW unit; Novos Power claims a direct MV-to-800 VDC unit with a 50% smaller footprint and air cooling; Eaton bought its way in by acquiring Resilient Power Systems; and more than $320M flowed into SST startups in the twelve months to March 2026[2]. NVIDIA's own four-stage timeline still places native SST deployments at the end of the queue, after sidecar and row-level 800 VDC — the transformer is the last piece to arrive, by design[1].
For facility planning purposes, the realistic reading of 2026 is this: 800 VDC racks and sidecars are procurement decisions; the SST is still an architecture decision, best exercised by designing the hall's DC segment so that a solid-state front end can replace the LFT-plus-rectifier later without touching anything downstream of the bus.
The bottom line
The solid-state transformer is not a better transformer. It is the deletion of the transformer as a category — replaced by 21 stacked power converters that happen to include a ferrite core the size of a fist. The working principle is a three-stage chain: cascaded H-bridge modules that survive the 11.3 kV phase peak by sharing it, dual active bridges that move power through a medium-frequency magnetic at 50-100 kHz with the transfer angle as the control variable, and an output bank that connects in parallel to create the 800 VDC bus directly — no inverter, and the UPS absorbed into the same link.
The measured numbers are real but narrow: 98.1% demonstrated at 25 kW in 2018, 98% at 400 kW in 2025, 99% as the product target, versus a conventional grey-space segment at 96.6% — worth about $17,000 per MW-year, and dwarfed by the controllability, footprint, and consolidation gains. The open items are equally concrete: no fleet reliability data, concentrated heat on an actively cooled critical path, a device roadmap the schedule depends on, and DC protection still being standardized. Between sidecars in 2026 and native SST halls at the end of NVIDIA's timeline, the engineering task for operators is not to bet on the SST but to keep the option open — a DC-segment design that a solid-state front end can drop into when the 99% units ship.
DC Build X supplies the distribution hardware on both sides of that future switch — busway, rack PDUs, containment, and the monitoring layer that makes the efficiency arithmetic verifiable in production. Request a quote with your hall's MV entry and rack plan, and we will size the 800 VDC distribution to accept whichever front end wins.
Related reading: the architecture this device plugs into is covered in NVIDIA 800 VDC power architecture: advantages for AI data centers; the grid-side power quality obligations the SST's controlled bridges partially absorb, in power quality and clean power; and the transient-sizing logic for the storage that rides the DC bus, in UPS battery backup sizing.
References
- NVIDIA Technical Blog, "NVIDIA 800 V HVDC Architecture Will Power the Next Generation of AI Factories," 2025. developer.nvidia.com
- SemiAnalysis, "Inside the 800VDC Revolution" — ETH Zurich 400 kW INTELEC 2025 benchmark, vendor landscape, displaced-capex estimates, reliability and device-roadmap analysis. newsletter.semianalysis.com
- D. Rothmund, T. Guillod, J. W. Kolar, ETH Zurich PES Laboratory, "Highly Efficient 10 kV SiC-Based Solid-State Transformers" — 25 kW, 3.8 kV AC to 400 V DC unit at 98.1% measured efficiency. pes-publications.ee.ethz.ch
- Navitas Semiconductor, "Redefining Data Center Power: GaN and SiC Technologies for Next-Gen 800 VDC Infrastructure" — ISOP SST reference architecture for 13.8/34.5 kV to 800 VDC. navitassemi.com
- Navitas Semiconductor, "Navitas Announces 3300V and 2300V UHV Silicon Carbide Product Portfolio," press release, 2026. nasdaq.com
- SolarEdge Technologies and Infineon Technologies, "SolarEdge and Infineon Collaborate to Advance High-Efficiency Power Infrastructure for AI Data Centers," Nov 5, 2025 — modular 2-5 MW SST building block, direct 13.8-34.5 kV to 800-1500 VDC, above 99% target. investors.solaredge.com
- Deep Intellica, "Solid-State Transformers and 800 V DC Architecture: Powering Next-Generation AI Data Centres" — three-stage architecture, NPC Electric 87 MWh/yr and 50% footprint figures. deepintellica.com
- IC Views (半导纵横), "800VDC, 凭什么颠覆传统 AI 机架供电?" — Infineon 40x weight / 14x size figures, 82-85% to 97% efficiency-path estimate, IEEE 1547/2800 DER implications, cooling approaches. icviews.cn
- HAIMEI Electric, "IEEE/ETH Solid-State Transformer (SST) AI Computing Power Initiative" — DAB phase-shift ZVS operation, MMC module redundancy, three-stage architecture summary. huameielectric.com